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| 19-3360; Rev 0; 8/04 Multiphase, Fixed-Frequency Controller for AMD Hammer CPU Core Power Supplies General Description The MAX8707 is a multiphase (3-/4-phase), interleaved, fixed-frequency, step-down controller for AMD Hammer CPU core supplies. Interleaved multiphase operation reduces the input ripple current and output voltage ripple while easing component selection and layout placement. The MAX8707 includes active voltage positioning with adjustable gain and offset, reducing power dissipation and bulk output-capacitance requirements. The MAX8707 is intended for two different notebook CPU core applications: stepping down the battery directly or stepping down the +5V system supply to create the core voltage. The single-stage conversion method allows these devices to directly step down high-voltage batteries for the highest possible efficiency. Alternatively, 2-stage conversion (stepping down the +5V system supply instead of the battery) at higher switching frequency provides the minimum possible physical size. The MAX8707 features dedicated differential currentsense inputs for each phase and includes a fifth pair of current-sense inputs to provide an accurate voltagepositioning slope and average current-limit protection using a single current-sense resistor. The MAX8707 also has two dedicated inputs that provide differential remote voltage sensing. The MAX8707 provides an analog input for setting the suspend voltage and a slew-rate controller for transitions between VID codes or the suspend voltage. The controllers reduce the transition slew rate during startup and shutdown, providing soft-start with minimal input surge current and damped soft-shutdown without negative output undershoot. The MAX8707 includes output fault protection--undervoltage, nonlatched overvoltage, and thermal overload--and an independent voltageregulator power-OK (VROK) output. The MAX8707 has a selectable switching frequency, allowing 200kHz, 300kHz, or 600kHz per-phase operation. The MAX8707 is available in the low-profile, 40-pin, 6mm x 6mm thin QFN package. Refer to the MAX8702/ MAX8703 for compatible drivers. Features o 3-/4-Phase Interleaved Fixed-Frequency Controller o 0.75% VOUT Accuracy Over Line, Load, and Temperature o 5-Bit On-Board Digital-to-Analog Converter (DAC)--0.80V to 1.55V o Adjustable Suspend Voltage Input o Active Voltage Positioning with Adjustable Gain and Offset o Accurate Lossless Current Balance o Accurate Droop and Current Limit o Remote Output and Ground Sense o Output Slew-Rate Control o Power-Good Window Comparator o Selectable 200kHz/300kHz/600kHz Switching Frequency o Output Overvoltage and Undervoltage Protection o Thermal Fault Protection o 2V 0.7% Reference Output o Soft-Startup and Shutdown MAX8707 Ordering Information PART MAX8707ETL TEMP RANGE -40C to +85C PIN-PACKAGE 40 Thin QFN 6mm x 6mm Applications AMD Hammer Desknote Computers Multiphase CPU Core Supplies Voltage-Positioned Step-Down Converters Notebook/Desktop Computers Servers Pin Configuration appears at end of data sheet. ________________________________________________________________ Maxim Integrated Products 1 For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com. Multiphase, Fixed-Frequency Controller for AMD Hammer CPU Core Power Supplies MAX8707 ABSOLUTE MAXIMUM RATINGS VCC to GND ..............................................................-0.3V to +6V D0-D4 to GND..........................................................-0.3V to +6V SKIP, SUS, VROK, ILIM(AVE) to GND......................-0.3V to +6V SUSV, OFS, OSC to GND.........................................-0.3V to +6V CSP_, CSN_, CRSP, CRSN to GND .........................-0.3V to +6V VPS, FBS, CCV, REF to GND .....................-0.3V to (VCC + 0.3V) ILIM(PK), TRC, TIME to GND .....................-0.3V to (VCC + 0.3V) PWM_, DRSKP to PGND ............................-0.3V to (VCC + 0.3V) PGND, GNDS to GND ...........................................-0.3V to +0.3V SHDN to GND (Note 1)...........................................-0.3V to +14V REF Short-Circuit Duration .........................................Continuous Continuous Power Dissipation (TA = +70C) 40-Pin 6mm x 6mm Thin QFN (derate 26.3mW/C above +70C) ................................2.105W Operating Temperature Range ...........................-40C to +85C Junction Temperature ......................................................+150C Storage Temperature Range .............................-65C to +150C Lead Temperature (soldering, 10s) .................................+300C Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Note 1: SHDN can be forced to 12V for debugging prototype boards using the no-fault test mode, which disables fault protection. ELECTRICAL CHARACTERISTICS (Circuit of Figure 1. VCC = VSHDN = 5V, OSC = REF, VVPS = VFBS = VCRSN = VCRSP = VCSP_ = 1.20V, VSUSV = 0.8V, OFS = SUS = GNDS = PGND = SKIP = GND, D0-D4 set for 1.20V (D0-D4 = 01110). TA = 0C to +85C, unless otherwise specified. Typical values are at TA = +25C.) PARAMETER PWM CONTROLLER Input Voltage Range VCC Includes loadregulation error (VPS = FBS) DAC codes from 1.10V to 1.55V DAC codes from 0.80V to 1.075V SUS = VCC SUSV Input Range SUSV Input-Bias Current OFS Input Range VSUSV ISUSV VOFS VSUSV = 0.4V to 2V Negative offsets Positive offsets VOUT / VOFS, VOFS = VOFS, VOFS = 0 to 0.8V VOUT / VOFS, VOFS = VOFS-VREF, VOFS = 1.2V to 2V VOFS = 0 to 2V VOUT / VGNDS, -200mV VGNDS +200mV CRSP = CRSN, CSP_ = CSN_ OSC = GND Switching Frequency Accuracy (Per Phase) fSW OSC = REF OSC = VCC 4.5 -0.75 -2.0 -20 0.4 -0.1 0 1.2 -0.131 -0.131 -0.1 -200 0.95 -2 -10 180 270 540 200 300 600 1.00 -0.125 -0.125 5.5 +0.75 % +2.0 +20 2.0 +0.1 0.8 2.0 -0.118 V/V -0.118 +0.1 +200 1.05 +2 +10 220 330 660 kHz A mV V/V A A mV V A V V SYMBOL CONDITIONS MIN TYP MAX UNITS DC Output Voltage Accuracy VOUT OFS GAIN AOFS OFS Input-Bias Current GNDS Input Range GNDS Gain GNDS Input-Bias Current FBS Input-Bias Current IOFS VGNDS AGNDS IGNDS IFBS 2 _______________________________________________________________________________________ Multiphase, Fixed-Frequency Controller for AMD Hammer CPU Core Power Supplies ELECTRICAL CHARACTERISTICS (continued) (Circuit of Figure 1. VCC = VSHDN = 5V, OSC = REF, VVPS = VFBS = VCRSN = VCRSP = VCSP_ = 1.20V, VSUSV = 0.8V, OFS = SUS = GNDS = PGND = SKIP = GND, D0-D4 set for 1.20V (D0-D4 = 01110). TA = 0C to +85C, unless otherwise specified. Typical values are at TA = +25C.) PARAMETER SYMBOL CONDITIONS RTIME = 143k (6.25mV/s) TIME Slew-Rate Accuracy RTIME = 47k (19mV/s) to 392k (2.28mV/s) Startup and shutdown, RTIME = 47k (4.75mV/s) to 392k (0.57mV/s) BIAS AND REFERENCE Quiescent Supply Current (VCC) Shutdown Supply Current (VCC) Reference Voltage Reference Load Regulation FAULT PROTECTION Measured at VPS with respect to unloaded output voltage, rising edge, 8mV hysteresis Minimum OVP level Output Overvoltage Propagation Delay Output Undervoltage-Protection Threshold Output Undervoltage Propagation Delay VROK Transition Blanking Time tOVP VUVP tUVP VPS forced 25mV above trip threshold Measured at VPS with respect to 70% of the unloaded nominal output voltage VPS forced 25mV below trip threshold Measured from the time when VPS reaches the target voltage, slew rate set by RTIME (Note 2) Undervoltage measured at VPS with respect to 87.5% unloaded output voltage, falling edge, 15mV hysteresis VROK Threshold Overvoltage measured at VPS with respect to 112.5% of the unloaded output voltage, rising edge, 15mV hysteresis VROK Delay VROK Output Low Voltage VROK Leakage Current tVROK VPS forced 25mV outside the VROK trip thresholds ISINK = 3mA High state, VROK forced to 5.5V -30 +30 -30 10 PWM (SKIP = GND) or SKIP mode when VOUT VTRIP SKIP = VCC and VOUT > VTRIP 150 200 250 mV ICC ICC(SHDN) VREF VREF Measured at VCC, VPS and FBS forced above the regulation points Measured at VCC, SHDN = GND VCC = 4.5V to 5.5V, IREF = 0 IREF = 0 to 500A IREF = -100A to 0 1.986 -2 7 0.05 2.000 -0.2 0.21 6.2 12 10 2.014 mA A V mV MIN -10 -15 -20 TYP MAX +10 +15 +20 % UNITS MAX8707 Output Overvoltage-Protection Threshold VOVP 1.70 1.75 1.1 10 1.80 V s +30 mV s tBLANK 20 s -30 +30 mV 10 0.4 1 s V A _______________________________________________________________________________________ 3 Multiphase, Fixed-Frequency Controller for AMD Hammer CPU Core Power Supplies MAX8707 ELECTRICAL CHARACTERISTICS (continued) (Circuit of Figure 1. VCC = VSHDN = 5V, OSC = REF, VVPS = VFBS = VCRSN = VCRSP = VCSP_ = 1.20V, VSUSV = 0.8V, OFS = SUS = GNDS = PGND = SKIP = GND, D0-D4 set for 1.20V (D0-D4 = 01110). TA = 0C to +85C, unless otherwise specified. Typical values are at TA = +25C.) PARAMETER VCC Undervoltage-Lockout Threshold Thermal-Shutdown Threshold DC Droop Amplifier Offset DC Droop Amplifier Transconductance (CRS Sense Enabled) DC Droop Amplifier Transconductance (CRS Sense Disabled) Gm(VPS) IVPS / (N x VCRS), VVPS = VCRSN = 1.2V, VCRSP - VCRSN = -60mV to +60mV, N = number of phases enabled IVPS / (VCS), VCRSP = VCC, VVPS = VCSN_ = 1.2V, VCSP_ - VCSN_ = -60mV to +60mV Current-sense gain (ACS = 10 typ) divided by the voltage preamplifier transconductance (Gm(TRC) = 2ms typ) Measured at VPS with respect to steadystate VPS regulation voltage; falling edge, 5.5mV hysteresis (typ) SYMBOL VUVLO(VCC) TSHDN CONDITIONS Rising edge, hysteresis = 20mV, PWM_ disabled below this level Rising edge hysteresis = 15C -1.5 194 200 MIN 4.10 TYP 4.25 +160 +1.5 206 MAX 4.45 UNITS V C mV S DROOP AND TRANSIENT RESPONSE Gm(VPS) 194 200 206 S Transient-Droop Transresistance RTRANS 4.75 5.0 5.25 k Transient Detection Threshold CURRENT LIMIT AND BALANCE Current-Sense Input Preamplifier Offsets ILIM(AVE) Input Range (Adjustable Mode) ILIM(AVE) Average Current-Limit Threshold Voltage (Positive, Default) ILIM(AVE) Average Current-Limit Threshold Voltage (Positive, Adjustable) ILIM(AVE) Average Current-Limit Threshold Voltage (Negative) ILIM(AVE) Input Current ILIM(AVE) Current-Limit Default Switchover Threshold ILIM(PK) Peak Current-Limit Threshold Voltage (Positive) ILIM(PK) Peak Current-Limit Threshold Voltage (Negative) VPKLIMIT IILIM(AVE) VILIM(AVE) -30 -25 -20 mV CSP_ - CSN_ -2.0 VREF - 1.0 +2.0 VREF - 0.2 25 28 mV V VAVELIMIT CRSP - CRSN; ILIM(AVE) = VCC VILIM(AVE) = VREF - 0.2V 22 mV 7 46 -30 -0.1 3 10 50 -25 13 mV 54 -20 +0.1 mV A V VAVELIMIT CRSP - CRSN VILIM(AVE) = VREF - 1.0V CRSP - CRSN; ILIM(AVE) = VCC VCC - 1.0 30 50 -50 VCC - 0.4 36 CSP_ - CSN_, RILIM(PK) = RTRC x 8V / VLIM(PK) VPKLIMIT = 30mV VPKLIMIT = 50mV 24 40 -60 mV 60 -40 mV CSP_ - CSN_, RILIM(PK) = RTRC x 8V / VPKLIMIT, VPKLIMIT = 50mV 4 _______________________________________________________________________________________ Multiphase, Fixed-Frequency Controller for AMD Hammer CPU Core Power Supplies MAX8707 ELECTRICAL CHARACTERISTICS (continued) (Circuit of Figure 1. VCC = VSHDN = 5V, OSC = REF, VVPS = VFBS = VCRSN = VCRSP = VCSP_ = 1.20V, VSUSV = 0.8V, OFS = SUS = GNDS = PGND = SKIP = GND, D0-D4 set for 1.20V (D0-D4 = 01110). TA = 0C to +85C, unless otherwise specified. Typical values are at TA = +25C.) PARAMETER ILIM(PK) Idle Current-Limit Threshold Voltage (Skip Mode) Current-Sense Input Current Current-Sense Common-Mode Input Range Phase Disable Threshold CRS Sense Input Disable Threshold LOGIC AND I/O Logic Input High Voltage Logic Input Low Voltage SHDN No-Fault Threshold D0-D4 Logic Input High Voltage D0-D4 Logic Input Low Voltage High (VCC) OSC 3-Level Input Logic Levels VOSC Medium (REF) Low (GND) SKIP Input Logic Levels Logic Input Current Logic Output High Voltage Logic Output Low Voltage VOH VOL VSKIP High Low (GND) SHDN, SKIP, SUS, OSC, D0-D4 = 0 to 5V PWM_, DRSKP; ISOURCE = 3mA PWM_, DRSKP; ISINK = 3mA -1 VCC 0.4 0.4 1.2 0.8 +1 VCC 0.4 1.8 2.2 0.4 V A V V V VIH VIL SHDN, SUS SHDN, SUS To enable no-fault mode 11 0.8 0.4 2.4 0.8 13 V V V V V SYMBOL VIDLE CONDITIONS CSP_ - CSN_, VSKIP 1.2V, RILIM(PK) = RTRC x 8V / VPKLIMIT, VPKLIMIT = 50mV CSP_, CRSP CSN_, CRSN CRSP, CRSN, CSP_, CSN_ CSP4 CRSP MIN 2 -0.2 -1.0 0 3 3 VCC - 1 VCC - 1 TYP 5 MAX 8 +0.2 +1.0 2 VCC 0.4 VCC 0.4 UNITS mV A V V V _______________________________________________________________________________________ 5 Multiphase, Fixed-Frequency Controller for AMD Hammer CPU Core Power Supplies MAX8707 ELECTRICAL CHARACTERISTICS (Circuit of Figure 1. VCC = VSHDN = 5V, OSC = REF, VVPS = VFBS = VCRSN = VCRSP = VCSP_ = 1.20V, VSUSV = 0.8V, OFS = SUS = GNDS = PGND = SKIP = GND, D0-D4 set for 1.20V (D0-D4 = 01110). TA = -40C to +85C, unless otherwise specified.) (Note 3) PARAMETER PWM CONTROLLER Input Voltage Range VCC Includes loadregulation error (VPS = FBS) DAC codes from 1.10V to 1.55V DAC codes from 0.80V to 1.075V SUS = VCC SUSV Input Range OFS Input Range VSUSV VOFS Negative offsets Positive offsets VOUT / VOFS; VOFS = VOFS, VOFS = 0 to 0.8V VOUT / VOFS; VOFS = VOFS - VREF, VOFS = 1.2V to 2V VOUT / VGNDS, -200mV VGNDS +200mV OSC = GND Switching Frequency Accuracy (Per Phase) fSW OSC = REF OSC = VCC RTIME = 143k (6.25mV/s) TIME Slew-Rate Accuracy RTIME = 47k (19mV/s) to 392k (2.28mV/s) Startup and shutdown, RTIME = 47k (4.75mV/s) to 392k (0.57mV/s) BIAS AND REFERENCE Quiescent Supply Current (VCC) Shutdown Supply Current (VCC) Reference Voltage Reference Load Regulation FAULT PROTECTION Measured at VPS with respect to unloaded output voltage, rising edge, 8mV hysteresis PWM (SKIP = GND) or SKIP mode when VOUT VTRIP SKIP = VCC and VOUT > VTRIP 150 250 mV ICC ICC(SHDN) VREF VREF Measured at VCC, VPS and FBS forced above the regulation points Measured at VCC, SHDN = GND VCC = 4.5V to 5.5V, IREF = 0 IREF = 0 to 500A IREF = -100A to 0 1.98 -2 6.2 12 10 2.02 mA A V mV mV 4.5 -1.0 -3.0 -25 0.4 0 1.2 -0.131 -0.131 -200 0.95 180 270 540 -10 -15 -20 5.5 +1.0 % +3.0 +25 2.0 0.8 2.0 -0.118 V/V -0.118 +200 1.05 220 330 660 +10 +15 +20 % kHz mV V/V mV V V V SYMBOL CONDITIONS MIN MAX UNITS DC Output Voltage Accuracy VOUT OFS GAIN AOFS GNDS Input Range GNDS Gain VGNDS AGNDS Output Overvoltage-Protection Threshold VOVP 1.70 1.80 V 6 _______________________________________________________________________________________ Multiphase, Fixed-Frequency Controller for AMD Hammer CPU Core Power Supplies MAX8707 ELECTRICAL CHARACTERISTICS (continued) (Circuit of Figure 1. VCC = VSHDN = 5V, OSC = REF, VVPS = VFBS = VCRSN = VCRSP = VCSP_ = 1.20V, VSUSV = 0.8V, OFS = SUS = GNDS = PGND = SKIP = GND, D0-D4 set for 1.20V (D0-D4 = 01110). TA = -40C to +85C, unless otherwise specified.) (Note 3) PARAMETER Output Undervoltage-Protection Threshold SYMBOL VUVP CONDITIONS Measured at VPS with respect to 70% of the unloaded nominal output voltage Undervoltage, measured at VPS with respect to 87.5% of the unloaded output voltage, falling edge, 15mV hysteresis VROK Threshold Overvoltage, measured at VPS with respect to 112.5% of the unloaded output voltage, rising edge, 15mV hysteresis VROK Output Low Voltage VCC Undervoltage-Lockout Threshold DC Droop Amplifier Offset DC Droop Amplifier Transconductance (CRS Sense Enabled) DC Droop Amplifier Transconductance (CRS Sense Disabled) Gm(VPS) IVPS / (N x VCRS); VVPS = VCRSN = 1.2V, VCRSP - VCRSN = -60mV to +60mV, N = number of phases enabled IVPS / (VCS), VCRSP = VCC, VVPS = VCSN_ = 1.2V, VCSP_ - VCSN_ = -60mV to +60mV Current-sense gain (ACS = 10 typ) divided by the voltage preamplifier transconductance (Gm(TRC) = 2mS typ) ISINK = 3mA Rising edge, hysteresis = 20mV, PWM_ VUVLO(VCC) disabled below this level 4.10 -40 +40 0.4 4.45 V V MIN -40 MAX +40 UNITS mV -40 +40 mV DROOP AND TRANSIENT RESPONSE -2 190 +2 210 mV S Gm(VPS) 190 210 S Transient-Droop Transresistance CURRENT LIMIT AND BALANCE Current-Sense Input Preamplifier Offsets ILIM(AVE) Input Range (Adjustable Mode) ILIM(AVE) Average Current-Limit Threshold Voltage (Positive, Default) ILIM(AVE) Average Current-Limit Threshold Voltage (Positive, Adjustable) ILIM(AVE) Average Current-Limit Threshold Voltage (Negative) ILIM(AVE) Current-Limit Default Switchover Threshold RTRANS 4.50 5.25 k CSP_ - CSN_ VILIM(AVE) -2.5 VREF - 1.0 +2.5 VREF - 0.2 30 mV V VAVELIMIT CRSP - CRSN; ILIM(AVE) = VCC 20 mV VILIM(AVE) = VREF - 0.2V VAVELIMIT CRSP - CRSN VILIM(AVE) = VREF - 1.0V CRSP - CRSN; ILIM(AVE) = VCC 5 44 -31 3 15 mV 56 -19 VCC - 0.4 mV V _______________________________________________________________________________________ 7 Multiphase, Fixed-Frequency Controller for AMD Hammer CPU Core Power Supplies MAX8707 ELECTRICAL CHARACTERISTICS (continued) (Circuit of Figure 1. VCC = VSHDN = 5V, OSC = REF, VVPS = VFBS = VCRSN = VCRSP = VCSP_ = 1.20V, VSUSV = 0.8V, OFS = SUS = GNDS = PGND = SKIP = GND, D0-D4 set for 1.20V (D0-D4 = 01110). TA = -40C to +85C, unless otherwise specified.) (Note 3) PARAMETER ILIM(PK) Peak Current-Limit Threshold Voltage (Positive) SYMBOL VPKLIMIT CONDITIONS CSP_ - CSN_, RILIM(PK) = RTRC x 8V / VLIM(PK) VPKLIMIT = 30mV VPKLIMT = 50mV MIN 24 40 MAX 36 mV 60 UNITS ILIM(PK) Peak Current-Limit Threshold Voltage (Negative) CSP_ - CSN_, RILIM(PK) = RTRC x 8V / VPKLIMIT, VPKLIMIT = 50mV VIDLE CSP_ - CSN_, VSKIP 1.2V, RILIM(PK) = RTRC x 8V / VPKLIMIT, VPKLIMIT = 50mV CSP_, CRSP CSN_, CRSN CRSP, CRSN, CSP_, CSN_ CSP4 CRSP -60 -40 mV ILIM(PK) Idle Current-Limit Threshold Voltage (Skip Mode) Current-Sense Input Current Current-Sense Common-Mode Input Range Phase Disable Threshold CRS Sense Input Disable Threshold LOGIC AND I/O Logic Input High Voltage Logic Input Low Voltage D0-D4 Logic Input High Voltage D0-D4 Logic Input Low Voltage 2 -0.2 -1.0 0 3 3 8 +0.2 +1.0 2 VCC - 0.4 VCC - 0.4 mV A V V V VIH VIL SHDN, SUS SHDN, SUS 2.4 0.8 0.8 0.4 VCC - 0.4 1.8 1.2 0.8 VCC - 0.4 2.2 0.4 V V V V High (VCC) OSC 3-Level Input Logic Levels VOSC Medium (REF) Low (GND) SKIP Input Logic Levels Logic Output High Voltage VSKIP VOH High Low (GND) PWM_, DRSKP; ISOURCE = 3mA V V V Note 2: VROK is blanked during the transitions, when the internal target is being slewed. See the Output-Voltage Transition Timing section. VROK is reenabled in tBLANK (20s) after the transition is completed. Note 3: Specifications to TA = -40C are guaranteed by design and are not production tested. 8 _______________________________________________________________________________________ Multiphase, Fixed-Frequency Controller for AMD Hammer CPU Core Power Supplies MAX8707 Typical Operating Characteristics (Circuit of Figure 1. VIN = 12V, VCC = 5V, SUS = SKIP = GND, SHDN = VCC, VSUSV = 0.80V, TA = +25C, unless otherwise specified.) EFFICIENCY vs. LOAD CURRENT (VOUT = 1.525V) MAX8707 toc01 EFFICIENCY vs. LOAD CURRENT (VOUT = 1.300V) MAX8707 toc02 EFFICIENCY vs. LOAD CURRENT (VOUT = 1.000V) VIN = 8V MAX8707 toc03 100 VIN = 8V 90 EFFICIENCY (%) 100 VIN = 8V 90 EFFICIENCY (%) 100 90 EFFICIENCY (%) 80 VIN = 12V 80 VIN = 12V 80 VIN = 12V 70 VIN = 20V 60 70 VIN = 20V 70 VIN = 20V 60 60 50 1 10 LOAD CURRENT (A) 100 50 1 10 LOAD CURRENT (A) 100 50 1 10 LOAD CURRENT (A) 100 OUTPUT VOLTAGE DEVIATION vs. LOAD CURRENT MAX8707 toc04 SINGLE-PHASE EFFICIENCY vs. LOAD CURRENT (VOUT = 0.800V) MAX8707 toc05 20 VIN = 12V 0 OUTPUT VOLTAGE (mV) -20 VOUT = 1.00V -40 -60 VOUT = 1.30V -80 -100 -120 0 20 40 LOAD CURRENT (A) 60 90 EFFICIENCY (%) VIN = 8V VIN = 12V IBIAS SUPPLY CURRENT (mA) 150 80 100 IIN 70 VIN = 20V 60 SKIP = SUS = VCC 0.1 1 10 100 50 SKIP = VCC 0 0 5 10 15 20 25 INPUT VOLTAGE (V) 50 80 LOAD CURRENT (A) NO-LOAD SUPPLY CURRENT vs. INPUT VOLTAGE (1-PHASE PULSE SKIPPING) MAX8707 toc07 OUTPUT OFFSET VOLTAGE vs. OFS VOLTAGE MAX8707 toc08 REFERENCE VOLTAGE DISTRIBUTION SAMPLE SIZE = 100 SAMPLE PERCENTAGE (%) 40 MAX8707 toc09 10 SKIP = GND 8 SUPPLY CURRENT (mA) IBIAS 6 150 OUTPUT OFFSET VOLTAGE (mV) 100 50 0 -50 -100 -150 50 30 4 20 2 IIN = 15A 0 0 5 10 15 20 25 INPUT VOLTAGE (V) 10 UNDEFINED REGION 0 0.5 1.0 OFS VOLTAGE (V) 1.5 2.0 0 1.990 1.995 2.000 2.005 2.010 REFERENCE VOLTAGE (V) _______________________________________________________________________________________ MAX8707 toc06 100 NO-LOAD SUPPLY CURRENT vs. INPUT VOLTAGE (4-PHASE FORCED-PWM MODE) 200 9 Multiphase, Fixed-Frequency Controller for AMD Hammer CPU Core Power Supplies MAX8707 Typical Operating Characteristics (Circuit of Figure 1. VIN = 12V, VCC = 5V, SUS = SKIP = GND, SHDN = VCC, VSUSV = 0.80V, TA = +25C, unless otherwise specified.) OUTPUT OFFSET VOLTAGE DISTRIBUTION MAX8707 toc10 VPS TRANSCONDUCTANCE DISTRIBUTION MAX8707 toc11 CURRENT-SENSE VOLTAGE DIFFERENCE vs. LOAD CURRENT 0.5 0.4 0.3 0.2 0.1 0 -0.1 -0.2 MAX8707 toc12 50 0.800V 1.550V SAMPLE PERCENTAGE (%) 40 SAMPLE SIZE = 100 70 SAMPLE SIZE = 100 60 SAMPLE PERCENTAGE (%) 50 40 30 20 10 0 0.6 CURRENT-SENSE DIFFERENCE (mV) 30 20 10 0 -5 -3 -1 1 3 5 OUTPUT OFFSET VOLTAGE (mV) 195 197 199 201 203 205 0 5 10 15 20 25 TRANSCONDUCTANCE (S) LOAD CURRENT (A) STARTUP WAVEFORM (NO LOAD) MAX8707 toc13 STARTUP WAVEFORM (20A LOAD) MAX8707 toc14 SHUTDOWN WAVEFORM (NO LOAD) MAX8707 toc15 3.3V 0 5V 0 2V 0 1V 0 A B C D E F G 200s/div A. SHDN, 5V/div B. DRSKP, 10V/div C. REF, 2V/div D. OUT, 1V/div E. VROK, 10V/div F. DL1, 10V/div G. INDUCTOR CURRENT (IL1), 10A/div 3.3V 0 5V 0 2V 0 1V 0 A B C D E F G 200s/div A. SHDN, 5V/div B. DRSKP, 10V/div C. REF, 2V/div D. OUT, 1V/div E. VROK, 10V/div F. DL1, 10V/div G. INDUCTOR CURRENT (IL1), 10A/div 3.3V 0 5V 0 1.3V 0 A B C D 0 200s/div A. SHDN, 5V/div B VROK, 10V/div C. OUT, 1V/div E D. DL1, 10V/div E. INDUCTOR CURRENT (IL1), 10A/div 10 ______________________________________________________________________________________ Multiphase, Fixed-Frequency Controller for AMD Hammer CPU Core Power Supplies MAX8707 Typical Operating Characteristics (continued) (Circuit of Figure 1. VIN = 12V, VCC = 5V, SUS = SKIP = GND, SHDN = VCC, VSUSV = 0.80V, TA = +25C, unless otherwise specified.) LOAD TRANSIENT (VOUT = 1.30V) 65A A 10A 1.00V 1.30V 12V C 0 20A 10A 0 20s/div A. IOUT = 10A TO 65A, 50A/div B. VOUT, 100mV/div C. LX1, 10V/div D. INDUCTOR CURRENT (IL1), 10A/div A. IOUT = 0 TO 30A, 50A/div B. VOUT, 50mV/div 20s/div C. LX1, 10V/div D. INDUCTOR CURRENT (IL1), 10A/div A. IOUT = 0 TO 70A, 100A/div B. VOUT, 100mV/div 2s/div C. LX1, 10V/div D. INDUCTOR CURRENT (IL1), 10A/div D 0 10A 0 D B 12V C 0 20A 10A 0 VIN = 20V D B 20V C MAX8707 toc16 LOAD TRANSIENT (VOUT = 1.00V) 30A 0 TRANSIENT PHASE REPEAT MAX8707 toc17 MAX8707 toc18 70A A 0A 1.30V B A DEEP-SLEEP TRANSITION MAX8707 toc19 SUSPEND EXIT TRANSITION MAX8707 toc20 SUSPEND TRANSITION (SKIP = SUS) MAX8707 toc21 3.3V 0 0.2V 0 1.300V 1.275V 5A 5A IOUT = 20A 20s/div A. DPSLP, 5V/div B. OFS, 200mV/div C. VOUT, 25mV/div A 3.3V 0 1.30V A 3.3V 0 1.30V A B C B 0.80V 5V 0 0.80V C 5V 0 D B C D E E 20s/div D. INDUCTOR CURRENT (IL1), 10A/div E. INDUCTOR CURRENT (IL3), 10A/div A. SUS, 5V/div B. VOUT, 500mV/div C. DRSKP, 5V/div D. INDUCTOR CURRENT (IL1), 10A/div E. INDUCTOR CURRENT (IL3), 10A/div 200s/div A. SUS, 5V/div B. VOUT, 500mV/div C. DRSKP, 5V/div D E D. INDUCTOR CURRENT (IL1), 10A/div E. INDUCTOR CURRENT (IL3), 10A/div ______________________________________________________________________________________ 11 Multiphase, Fixed-Frequency Controller for AMD Hammer CPU Core Power Supplies MAX8707 Typical Operating Characteristics (continued) (Circuit of Figure 1. VIN = 12V, VCC = 5V, SUS = SKIP = GND, SHDN = VCC, VSUSV = 0.80V, TA = +25C, unless otherwise specified.) SUSPEND TRANSITION (SKIP = SUS) MAX8707 toc22 SUSPEND TRANSITION (SKIP = GND) MAX8707 toc23 D1 (25mV) VID TRANSITION MAX8707 toc24 3.3V 0 1.30V 0.80V 5V 0 A 3.3V 0 1.30V A 3.3V 0 B 1.30V C 1.275V 0 D B A B 0.80V 5V 0 C C D D E E 100s/div A. SUS, 5V/div B. VOUT, 500mV/div C. DRSKP, 5V/div D. INDUCTOR CURRENT (IL1), 10A/div E. INDUCTOR CURRENT (IL3), 10A/div A. SUS, 5V/div B. VOUT, 500mV/div C. DRSKP, 5V/div 40s/div D. INDUCTOR CURRENT (IL1), 10A/div E. INDUCTOR CURRENT (IL3), 10A/div A. D1, 5V/div B. VOUT, 25mV/div 0 20s/div C. INDUCTOR CURRENT (IL1), 10A/div D. INDUCTOR CURRENT (IL3), 10A/div D3 (200mV) VID TRANSITION MAX8707 toc25 3.3V 0 1.30V 1.10V 0 0 C D A B 20s/div A. D3, 5V/div B. VOUT, 200mV/div C. INDUCTOR CURRENT (IL1), 10A/div D. INDUCTOR CURRENT (IL3), 10A/div 12 ______________________________________________________________________________________ Multiphase, Fixed-Frequency Controller for AMD Hammer CPU Core Power Supplies MAX8707 Pin Description PIN NAME FUNCTION Low-Voltage VID DAC Code Input. The D0-D4 inputs do not have internal pullups. These 1.0V logic inputs are designed to interface directly with the CPU. In normal mode (Table 4, SUS = GND), the output voltage is set by the VID code indicated by the logic-level voltages on D0-D4. In suspend mode (SUS = high), the output voltage tracks the voltage at SUSV. Low-Voltage VID DAC Code Input Low-Voltage VID DAC Code Input (MSB) No Connect. Leave open. Pin internally connected. Pulse-Skipping Indicator Input. When pulse skipping, the controller blanks the VROK upper threshold. 3.3V or VCC (high) = 1-phase pulse-skipping operation (phases 2, 3, and 4 disabled) GND = multiphase forced-PWM operation The controller automatically enters forced-PWM mode during startup, shutdown, and the no-CPU VID mode. Shutdown Control Input. This input cannot withstand the battery voltage. Connect to VCC for normal operation. Connect to ground to put the IC into its 50nA (typ) shutdown state. During the startup and shutdown transitions, the output voltage is ramped at 1/4th the output-voltage slew rate programmed by RTIME. After completing soft-shutdown, the drivers are disabled--DRSKP and PWM_ are pulled low. Forcing SHDN to 11V~13V disables both overvoltage-protection and undervoltage-protection circuits, and clears the fault latch. Do not connect SHDN to >13V. Suspend Control Input. When the controller detects a transition on SUS, the controller slews the output voltage to the new voltage level determined by SUSV (SUS = high) or D0-D4 (SUS = low). The controller blanks VROK during the transition and another 20s after the new target voltage is reached. When SUS is high, the offset (OFS) is automatically disabled. Suspend-Mode Voltage Input. Connect to the output of a resistive voltage-divider from REF to GND to provide an analog voltage between 0.4V to 2V. The output voltage is set by the voltage at SUSV when SUS is high. 1 D2 2 3 4 D3 D4 N.C. 5 SKIP 6 SHDN 7 SUS 8 SUSV 9 Average Current-Limit Threshold Adjustment. The controller uses the accurate CRSP-to-CRSN currentsense voltage to limit the average current per phase. When the average current-limit threshold is exceeded, the controller internally reduces the peak inductor current-limit threshold (ILIM(PK)) at 2% of IPKLIMIT per s until the average current remains within the programmed limits. When the accurate current sensing is disabled (CRSP = VCC), the average current-limit circuit is disabled and ILIM(AVE) should be ILIM(AVE) connected to VCC. The average current-limit threshold defaults to 25mV if ILIM(AVE) is connected to VCC. In adjustable mode, the average current-limit threshold voltage is precisely 1/20th the voltage difference between ILIM(AVE) and the reference: (VREF - VILIM(AVE)) / 20 for a range of 1.0V (VREF - 1V) to 1.8V (VREF - 0.2V). The logic threshold for switchover to the 25mV default value is approximately VCC - 1V. Adjustable Offset Voltage Input. For 0 < VOFS < 0.8V, 1/8th the voltage at OFS is subtracted from the output. For 1.2V < VOFS < 2.0V, 1/8th the difference between REF and OFS is added to the output. Voltages in the range of 0.8V < VOFS < 1.2V are undefined. The controller disables the offset amplifier during suspend mode (SUS = high). 10 OFS ______________________________________________________________________________________ 13 Multiphase, Fixed-Frequency Controller for AMD Hammer CPU Core Power Supplies MAX8707 Pin Description (continued) PIN 11 NAME OSC FUNCTION Oscillator Select Input. OSC is a 3-level logic input for selecting the per-phase switching frequency. Connect to GND for 200kHz, connect to REF for 300kHz, or connect to VCC for 600kHz per phase. Ground Remote-Sense Input. Connect GNDS directly to the CPU ground-sense pin. GNDS internally connects to an amplifier that adjusts the output voltage, compensating for voltage drops from the regulator ground to the load ground. Slew-Rate Adjustment Pin. Connect a resistor from TIME to GND to set the internal slew rate. A 47k to 392k corresponds to slew rates of 19mV/s to 2.28mV/s, respectively, for all suspend voltage transitions. 13 TIME 12 GNDS t TRAN(SUS) = | VNEW - VOLD | dVTARGET / dt where dVTARGET / dt = 6.25mV/s x 143k / RTIME is the slew rate. For soft-start and shutdown, the controller automatically reduces the slew rate by 1/4th. For all dynamic VID transitions, the rate at which the VID inputs (D0-D4) are clocked sets the slew rate, as long as it is less than the dv/dt set by RTIME. Peak Inductor Current-Limit Threshold Adjustment (Cycle-by-Cycle Current Limit). If the voltage across the current-sense inputs (CSP to CSN) exceeds the peak current-limit threshold, the controller immediately terminates the respective phase's on-time. Connect a resistor RILIM(PK) from ILIM(PK) to GND to set the cycle-by-cycle peak current-limit threshold: 14 ILIM(PK) RILIM (PK ) = 8V x R TRC IPKLIMIT RCS where RCS is the resistance value of the current-sense element (inductors' DCR or current-sense resistor), RTRC is the resistance between TRC and REF, and IPKLIMIT is the desired peak current limit (per phase). 15 CCV Voltage Integrator Capacitor Connection. Connect a 470pF x (4 / PH) or greater capacitor from CCV to analog ground (GND) to set the integration time constant. Transient-Voltage Preamplifier Output. Connect a resistor (RTRC) between TRC and REF to set the transient droop based on the voltage-positioning requirements. TRC does not affect the DC steady-state droop. Choose RTRC based on the equation: 16 TRC R TRANSRCS R TRC = ACS PHRDROOP(AC) as defined in the Design Procedure (page 33). If voltage positioning is not required, RTRC is determined by the stability requirements. TRC is high impedance in shutdown. 14 ______________________________________________________________________________________ Multiphase, Fixed-Frequency Controller for AMD Hammer CPU Core Power Supplies MAX8707 Pin Description (continued) PIN NAME FUNCTION 2.0V Reference Output. Bypass to GND with a 0.22F to 1F (max) ceramic capacitor. The reference can source 500A for external loads. Loading REF degrades output-voltage accuracy according to the REF load-regulation error. Open-Drain Power-Good Output. After power-up, VROK remains high impedance as long as the output voltage remains in regulation. The controller blanks VROK (high impedance) whenever the slew-rate control is active (output-voltage transitions). VROK is forced low during startup and shutdown. In pulseskipping mode (SKIP = high), the upper VROK threshold is disabled. Analog Ground. Connect the MAX8707's exposed pad to analog ground. Power Ground. Ground connection for the driver control outputs (PWM_) and driver skip output (DRSKP). Analog Supply-Voltage Input. Connect VCC to the system supply voltage (4.5V to 5.5V) with a series 10 resistor. Bypass to analog GND with a 1F or greater ceramic capacitor, as close to the IC as possible. PWM Driver Control Output for Phase 1. Logic low in shutdown. PWM Driver Control Output for Phase 2. Logic low in shutdown. PWM Driver Control Output for Phase 3. Logic low in shutdown. PWM Driver Control Output for Phase 4. Logic low when disabled (CSP4 = VCC) and in shutdown. Driver Skip Control Output. Push/pull logic output that controls the operating mode of the skip-mode driver ICs. DRSKP swings from VCC to PGND. When DRSKP is high, the driver ICs operate in forced-PWM mode. When DRSKP is low, the driver ICs enable their zero-crossing comparators and operate in pulse-skipping mode. Remote Feedback Sense Input. Connect FBS to the CPU output sense point. To minimize output-voltage errors due to any resistance in series with the FBS input, the controller generates an FBS input bias current equal in magnitude and opposite in polarity to the VPS output current. FBS is high impedance in shutdown. Voltage-Positioning Transconductance-Amplifier Output. Connect a resistor RVPS between VPS and FBS to set the DC steady-state droop (load line) based on the required voltage-positioning slope (see the Voltage-Positioning Amplifier section). RVPS = RDROOP / (RSENSE x GM(VPS)) where RDROOP is the desired DC voltage-positioning slope, RSENSE is the current-sense resistor, and GM(VPS) = 200S. RSENSE is the accurate sense resistor used to generate current-sense voltage (CRSP, CRSN). When CRSP is connected to VCC, the input to the transconductance amplifier is the sum of the current-sense voltage (CSP_, CSN_) inputs. When the inductors' DC resistances (RDCR) are used as the current-sense elements (for lossless sensing), RVPS should include an NTC thermistor to minimize the temperature dependence of the voltage-positioning slope. To disable voltage positioning, short VPS to FBS. VPS is high impedance in shutdown. Negative Current-Sense Resistor Input. CRSN is the negative differential input used for accurate sensing of the phase 1 inductor current. Connect a current-sense resistor between CRSP and CRSN for accurate voltage positioning and current limit. Float CRSN when not used (CRSP pulled up to VCC). 17 REF 18 VROK 19 20 21 22 23 24 25 26 GND PGND VCC PWM1 PWM2 PWM3 PWM4 DRSKP 27 FBS 28 VPS 29 CRSN ______________________________________________________________________________________ 15 Multiphase, Fixed-Frequency Controller for AMD Hammer CPU Core Power Supplies MAX8707 Pin Description (continued) PIN NAME FUNCTION Positive Current-Sense Resistor Input. CRSP is the positive differential input used for accurate sensing of the phase 1 inductor current. Connect a current-sense resistor between CRSP and CRSN. If current-sense resistors are used on all phases (CSP_, CSN_), this additional current-sense (CRSP, CRSN) feature can be disabled by connecting CRSP to VCC and floating CRSN. Positive Current-Sense Input for Phase 1. This input should be connected to the positive terminal of the current-sense resistor or of the DCR sensing filtering capacitor, depending on the current-sense method implemented. Negative Current-Sense Input for Phase 1 Negative Current-Sense Input for Phase 2 Positive Current-Sense Input for Phase 2. This input should be connected to the positive terminal of the current-sense resistor or of the DCR sensing filtering capacitor, depending on the current-sense method implemented. Positive Current-Sense Input for Phase 3. This input should be connected to the positive terminal of the current-sense resistor or of the DCR sensing filtering capacitor, depending on the current-sense method implemented. Negative Current-Sense Input for Phase 3 Negative Current-Sense Input for Phase 4 Positive Current-Sense Input for Phase 4. This input should be connected to the positive terminal of the current-sense resistor or of the DCR sensing filtering capacitor, depending on the current-sense method implemented. Connect CSP4 to VCC for fixed 3-phase operation. Low-Voltage VID-DAC Code Inputs. The D0-D4 inputs do not have internal pullups. These 1.0V logic inputs are designed to interface directly with the CPU. In normal mode (Table 4, SUS = low), the output voltage is set by the D0-D4 VID-DAC inputs. In suspend mode (SUS = high), the output voltage tracks the voltage at SUSV. Low-Voltage VID-DAC Code Inputs 30 CRSP 31 32 33 34 CSP1 CSN1 CSN2 CSP2 35 36 37 38 CSP3 CSN3 CSN4 CSP4 39 D0 40 D1 Detailed Description +5V Bias Supply (VCC) The MAX8707 requires an external +5V bias supply in addition to the battery. Typically, this +5V bias supply is the notebook's 95%-efficient, +5V system supply. Keeping the bias supply external to the controller improves efficiency and eliminates the cost associated with the +5V linear regulator that would otherwise be needed to supply the PWM circuit and gate drivers. If stand-alone capability is needed, the +5V bias supply can be generated with an external linear regulator. The +5V bias supply must provide VCC (PWM controller) and VDRV (FET gate-drive power), so the maximum current drawn is: IBIAS = ICC + IDRIVE where ICC is provided in the Electrical Characteristics table and IDRIVE is the driver's supply current dominated by fSW x QG (per phase) as defined in the driver's data sheet. If the +5V bias supply is powered up prior to the battery supply, the enable signal (SHDN going from low to high) must be delayed until the battery voltage is present to ensure startup. 16 ______________________________________________________________________________________ Multiphase, Fixed-Frequency Controller for AMD Hammer CPU Core Power Supplies MAX8707 Switching Frequency (OSC) OSC is a 3-level logic input used to set the per-phase switching frequency. Connect OSC directly to GND, REF, or VCC for 200kHz, 300kHz, and 600kHz operation, respectively. High-frequency (600kHz, OSC = VCC) operation optimizes the application for the smallest component size, trading off efficiency due to higher switching losses. This may be acceptable in ultraportable devices where the load currents are lower. Low-frequency (200kHz, OSC = GND) operation offers the best overall efficiency at the expense of component size and board space. oscillator edges. This effectively triggers a phase a full cycle early, increasing the total inductor-current slew rate and providing an immediate transient response. Feedback-Adjustment Amplifiers Voltage-Positioning Amplifier (Steady-State Droop) The multiphase controllers include a transconductance amplifier for adding gain to the voltage-positioning sense path. The current-sense inputs differentially sense the voltage across either a single current-sense resistor (CRS sensing enabled) or the inductor's DCR (CRS sensing disabled). The VPS amplifier's input is generated by sensing either a single phase (CRS sensing) and multiplying by the number of active phases, or by summing the current-sense (CS_) inputs of all active phases (CRSP = VCC). The transconductance amplifier's output connects to the regulator's voltage-positioned feedback input (VPS), so the resistance between VPS and the output voltage-sense point (FBS) determines the voltage-positioning gain: VOUT = VTARGET - RVPS IVPS where the target voltage (VTARGET) is defined in the Nominal Output-Voltage Selection section, and the transconductance amplifier's output current (IVPS) is determined by the current-sense voltage and the number of active phases (PH): IVPS = PH (VCRSP - VCRSN) GM(VPS) when CRS sensing is enabled, or: IVPS = (VCSP_ - VCSN_) GM(VPS) when CRS sensing is disabled (CRSP = VCC). where G M(VPS) is typically 200S as defined in the Electrical Characteristics table. To avoid output-voltage errors caused by the VPS current flowing through parasitic trace resistance or feedback fliter resistance, a second transconductance amplifier generates an equal and opposite current on the FBS input. Disable voltage positioning by shorting VPS directly to FBS. Interleaved Multiphase Operation The MAX8707 interleaves all the active phases--resulting in out-of-phase operation that minimizes the input and output filtering requirements, reduces electromagnetic interference (EMI), and improves efficiency. The multiphase controller shares the current between multiple phases that operate 90 out-of-phase (4-phase operation) or 120 out-of-phase (3-phase operation). The highside MOSFETs do not turn on simultaneously during normal operation. The instantaneous input current is effectively reduced by the number of active phases, resulting in reduced input voltage ripple, ESR power loss, and RMS ripple current (see the Input-Capacitor Selection section). Therefore, the controller achieves high performance while minimizing the component count-- which reduces cost, saves board space, and lowers component power requirements--making the MAX8707 ideal for high-power, cost-sensitive applications. Transient Phase Repeat When a transient occurs, the response time of the controller depends on its ability to quickly respond to the output-voltage deviation and slew the inductor current to the new current level. Multiphase, fixed-frequency controllers typically respond only to the clock edge, resulting in a delayed response from the actual transient event. To eliminate this delay time, the MAX8707 includes transient phase repeat, which allows the controller to immediately respond when heavy load transients are detected. If the controller detects that the output voltage has dropped by 25mV, the transient detection comparator immediately retriggers the phase that completed its on-time last. The controller triggers the subsequent phases as normal--on the appropriate ______________________________________________________________________________________ 17 MAX8707 RVCC 10 VCC 5V BIAS 5V BIAS CVCC 1.0F CIN RCSP1 1.5k CCS1 0.22F NH1 VCC TSET RTSET1 AGND DH2 L2 CSN2 LX2 CCSN2 4700pF CCS2 0.22F RCSP3 1.5k PGND NL2 DL2 CSP2 RDRHOT 100k CVCC1 1.0F DH1 L1 LX1 RCRSENSE 1.0m NH2 NL1 DL1 MAX8702 CCSN1 4700pF RCRSP 100 RCRSN 100 BST1 BST2 VDD RVCC1 10 CVDD1 4.7F GND CSP1 CSN1 8V TO 20V PWR INPUT Figure 1. Standard MAX8707 AMD Hammer Application Circuit D0 D1 D2 D3 D4 SHDN SKIP RTRC 2.0k TRC REF CRSN CCRS 1000pF VRON CRSP Multiphase, Fixed-Frequency Controller for AMD Hammer CPU Core Power Supplies 18 MAX8707 ILIM(AVE) ROFS1 182k DRHOT SHDN SKIP PWM1 PWM2 OFS ROFS2 20k RILIM(PK) 200k CCV ILIM(PK) TIME RTIME 143k L3 CSN3 CCSN3 4700pF CCS3 0.22F LX1 RCSP3 1.5k NL3 L4 CSN4 RVPS 6.49k CSP4 PGND OUTPUT (CPU CORE SUPPLY) VPS FBS RFBS 10 CPU REMOTE-SENSE CONNECTIONS GNDS CCSN4 4700pF LX2 CCS4 0.22F RCSP4 1.5k NL4 DL2 PGND NH4 DL1 AGND DH2 NH3 CCCV 1000pF 8V TO 20V PWR INPUT CIN BST1 BST2 DH1 VDD VCC TSET PWM2 PWM1 DRSKP PWM3 PWM4 CVDD2 4.7F RVCC2 10 CVCC2 1.0F VROK OSC SUS SUSV RSUSV2 81k CSP3 VID INPUTS ON SKIP OFF (VRON) PWM CREF 0.22F RILIMAVE1 RILIMAVE2 49.9k 150k 5V RVROK 100k 3-LEVEL PIN DPRSLPVR REF MAX8702 RTSET2 ______________________________________________________________________________________ SKIP PWM1 PWM2 DRHOT SHDN VRON RSUSV1 120k RGNDS 10 CGNDS 1000pF CFBS 1000pF Multiphase, Fixed-Frequency Controller for AMD Hammer CPU Core Power Supplies Transient-Droop Amplifier The MAX8707 controller includes a transient-droop transconductance amplifier to handle the instantaneous load transients typical of CPU applications. The transient-droop amplifier sets the correct voltage-positioning slope during a load transient, complimenting the slower steady-state voltage-positioning amplifier. The currentsense inputs differentially sense the voltage across the CSP_ and CSN_ current-sense element (inductor's DCR or current-sense resistor). The transconductance amplifier's output connects to the regulator's transient-response input (TRC), so the resistance between TRC and the reference voltage (REF) determines the transient voltagepositioning gain as defined in the Multiphase, Fixed-Frequency Design Procedure section. If voltage positioning is not required, R DROOP is defined by the maximum output-voltage sag with the worst-case transient load (VOUT / IOUT) and is subject to stability requirements. TRC is high impedance in shutdown. Differential Remote Sense The multiphase controllers include differential, remotesense inputs to eliminate the effects of voltage drops down the PC board traces and through the processor's power pins. The MAX8707 GNDS amplifier adds an offset directly to the target voltage, adjusting the output voltage to counteract the voltage drop in the ground path. Connect the feedback sense (FBS), voltage-positioning resistor (RVPS), and ground-sense (GNDS) inputs directly to the processor's core supply remote- sense outputs. Integrator Amplifier An integrator amplifier forces the DC average of the VPS voltage to equal the target voltage. This transconductance amplifier integrates the feedback voltage and provides a fine adjustment to the regulation voltage (Figure 2), allowing accurate DC output-voltage regulation regardless of the output ripple voltage. The integrator amplifier has the ability to shift the output voltage by 100mV (typ). The differential input voltage range is at least 60mV total, including DC offset and AC ripple. The integration time constant can be set easily with an external compensation capacitor at the CCV pin. Use a 470pF x (4 / PH) or greater ceramic capacitor. The MAX8707 disables the integrator by connecting the amplifier inputs together at the beginning of all transitions done in pulse-skipping mode (SKIP = high). The integrator remains disabled until 20s after the transition is completed (the internal target settles) and the output is in regulation (edge detected on the error comparator). MAX8707 Table 1. Component Selection for Standard Multiphase Applications DESIGNATION MAX8707 AMD HAMMER COMPONENTS Circuit of Figure 1 Input Voltage Range VID Output Voltage (D4-D0) SUSV Suspend Voltage (SUS = High) Maximum Load Current Number of Phases (TOTAL) Inductor (Per Phase) Switching Frequency (Per Phase) High-Side MOSFET (NH, Per Phase) Low-Side MOSFET (NL, Per Phase) 7V to 24V 1.50V (D4-D0 = 00010) 0.80V 80A 4 phases (1) MAX8705 + (2) MAX8702 0.56H, 1.6m Panasonic ETQP4LR56WFC 300kHz (OSC = REF) Siliconix (1) Si7892DP Siliconix (2) Si7356DP (8) 10F, 25V TDK C3225X7R1E106M Taiyo Yuden TMK325BJ106MN (6) 330F, 2.5V, 9m Sanyo 2R5TPE330M9 1.0m Panasonic ERJM1WTJ1M0U Total Input Capacitance (CIN) Total Output Capacitance (COUT) Current-Sense Resistor (RSENSE) When voltage positioning is disabled (VPS = FBS), the transient droop must be less than the 80mV minimum adjustment range of the integrator amplifier to guarantee proper DC output-voltage accuracy. Offset Amplifier The multiphase controllers include a fifth amplifier used to add small offsets to the voltage-positioned load line. The offset amplifier sums directly with the target voltage, making the offset gain independent of the DAC code. This amplifier has the ability to offset the output by 100mV. The offset is adjusted using resistive voltage-dividers at the OFS input. For inputs from 0 to 0.8V, the offset amplifier adds a negative offset to the output that is equal to 1/8th the voltage appearing at the OFS input (VOFFSET = -0.125 x VOFS). For inputs from 1.2V 19 ______________________________________________________________________________________ Multiphase, Fixed-Frequency Controller for AMD Hammer CPU Core Power Supplies MAX8707 VCC REF GND REFOK D4 D3 D2 D1 D0 CHANGE DAC WINDOW COMPARATOR SUS REF (2.0V) UVLO RUN MAX8707 DECODER SKIP GM SUSV SUS SHDN FAULT CSLEW ERROR AMP REF x4 FBS x4 A = 10 TARGET TRC GM(TRC) REF PHASE ENABLE DETECT OSCILLATOR OFS TARGET GM GNDS R-TO-I CONVERTER TIME CSP_ CSN_ SKIP TRC CLAMP R-TO-I CONVERTER OSC ILIM(PK) ILIM(AVE) EA[4:1] CURRENTLIMIT COMPARATOR 25mV SUS RUN 4-PHASE FIXED-FREQ CURRENT-MODE PWM LOGIC PWM_ DRSKP CRSP DROOP 500k TRAN LOAD-TRANSIENT DETECT COMPARATOR VPS 160S CCV INTEGRATOR AMP CHANGE FAULT (UVP + THERMAL) TARGET PGOOD AND FAULT DETECT PGND CRSN VPS GM(VPS) VROK Figure 2. MAX8707 Functional Diagram 20 ______________________________________________________________________________________ Multiphase, Fixed-Frequency Controller for AMD Hammer CPU Core Power Supplies MAX8707 Table 2. Component Suppliers MANUFACTURER BI Technologies Central Semiconductor Coilcraft Coiltronics Fairchild Semiconductor International Rectifier Kemet Panasonic Sanyo Siliconix (Vishay) Sumida Taiyo Yuden TDK TOKO WEBSITE www.bitechnologies.com www.centralsemi.com www.coilcraft.com www.coiltronics.com www.fairchildsemi.com www.irf.com www.kemet.com www.panasonic.com www.secc.co.jp www.vishay.com www.sumida.com www.t-yuden.com www.component.tdk.com www.tokoam.com Table 3. Operating-Mode Truth Table SHDN SUS SKIP OFS OUTPUT VOLTAGE GND D0-D4 (no offset) D0-D4 (no offset) OPERATING MODE Low-Power Shutdown Mode. PWM_ outputs are forced low, and the controller is disabled. The supply current drops to 10A (max). Normal Operation. The no-load output voltage is determined by the selected VID DAC code (D0-D4, Table 4). Pulse-Skipping Operation. When SKIP is pulled high, the MAX8707 immediately enters pulse-skipping operation allowing automatic PWM/PFM switchover under light loads. The VROK upper threshold is blanked. Deep-Sleep Mode. The no-load output voltage is determined by the selected VID-DAC code (D0-D4, Table 4) plus the offset voltage set by OFS. Suspend Mode/One Phase Skip. The no-load output voltage is determined by the suspend voltage present on SUSV, overriding all other active modes of operation. Fault Mode. The fault latch has been set by either UVP or thermal shutdown. The controller remains in FAULT mode until VCC power is cycled or SHDN toggled. GND X X X VCC GND GND GND or REF VCC GND VCC GND or REF VCC GND X 0 to 0.8V or 1.2V to 2.0V D0-D4 (plus offset) VCC VCC X X SUSV (no offset) VCC X X X GND X = Don't Care ______________________________________________________________________________________ 21 Multiphase, Fixed-Frequency Controller for AMD Hammer CPU Core Power Supplies to 2V, the offset amplifier adds a positive offset to the output that is equal to 1/8th the difference between the reference voltage and the voltage appearing at the OFS input (VOFFSET = 0.125 x (VREF - VOFS)). With this scheme, the controller supports both positive and negative offsets with a single input. The piecewise lineartransfer function is shown in Figure 3. The regions of the transfer function below zero, above 2.0V, and between 0.8V and 1.2V are undefined. OFS inputs are disallowed in these regions, and the respective effects on the output are not specified. The controller disables the offset amplifier during suspend mode (SUS = high). MAX8707 OUTPUT OFFSET VOLTAGE vs. OFS INPUT VOLTAGE 200mV UNDEFINED REGION OUTPUT OFFSET VOLTAGE 100mV 0 -100mV Nominal Output-Voltage Selection The nominal no-load output voltage (VTARGET) is defined by the selected voltage reference (VID DAC or SUSV) plus the offset voltage and remote ground-sense adjustment (VGNDS) as defined in the following equation: VTARGET = VDAC + VOFFSET + VGNDS when SUS = GND where VDAC is the selected VID voltage during normal operation (SUS = low, Table 4), and VOFFSET is the offset voltage defined by the OFS pin (Figure 3). In suspend mode (SUS = high), the offset voltage amplifier is disabled and the target voltage tracks the SUSV input voltage: VTARGET = VSUSV + VGNDS when SUS = VCC The MAX8707 uses a multiplexer that selects from one of three different inputs (Figure 2)--the output of the VID DAC, the SUSV suspend voltage, or ground (controller disabled). On startup, the MAX8707 slews the target voltage from ground to either the decoded D0-D4 (SUS = low) voltage or the SUSV voltage (SUS = high). DAC Inputs (D0-D4) During normal forced-PWM operation (SUS = low), the DAC programs the output voltage using the D0-D4 inputs. D0-D4 are low-voltage (1.0V) logic inputs, designed to interface directly with the CPU. Do not leave D0-D4 unconnected. D0-D4 can be changed while the MAX8707 is active, initiating a transition to a new outputvoltage level. Change D0-D4 together, avoiding greater than 50ns skew between bits. Otherwise, incorrect DAC readings may cause a partial transition to the wrong voltage level followed by the intended transition to the correct voltage level, lengthening the overall transition time. The available DAC codes and resulting output voltages -200mV 0 0.5V 0.8V 1.0V 1.2V 1.5V 2.0V OFS VOLTAGE (VOFS) Figure 3. Output Offset Voltage vs. OFS Input Voltage are compatible with the AMD Hammer (Table 4) specifications. Suspend Mode When the processor enters low-power suspend mode, the processor sets the regulator to a lower output voltage to reduce power consumption. The MAX8707 includes a buffered suspend-voltage input (SUSV) and a digital SUS control input. The suspend voltage is adjusted with an external resistive voltage-divider from REF to SUSV to analog ground. The suspend-voltage adjustment range is from 0.4V to 2.0V (VREF). When the CPU suspends operation (SUS = high), the controller disables the offset amplifier, overrides the 5-bit VID-DAC code set by D0-D4, and slews the output voltage to the target voltage set by the SUSV voltage. During the transition, the MAX8707 blanks both VROK thresholds until 20s after the slew-rate controller reaches the suspend-mode voltage. Once the 20s timer expires, the MAX8707 (SKIP pulled low) automatically switches to the 1-phase, pulse-skipping control scheme, forces DRSKP low, and blanks the upper VROK threshold. Output-Voltage Transition Timing The MAX8707 performs mode transitions in a controlled manner, automatically minimizing input surge currents. This feature allows the circuit designer to achieve nearly 22 ______________________________________________________________________________________ Multiphase, Fixed-Frequency Controller for AMD Hammer CPU Core Power Supplies MAX8707 Table 4. AMD Hammer Output-Voltage VID DAC Codes (SUS = GND) D4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 D3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 D2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 D1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 D0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 OUTPUT VOLTAGE (V) 1.550 1.525 1.500 1.475 1.450 1.425 1.400 1.375 1.350 1.325 1.300 1.275 1.250 1.225 1.200 1.175 D4 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 D3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 D2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 D1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 D0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 OUTPUT VOLTAGE (V) 1.150 1.125 1.100 1.075 1.050 1.025 1.000 0.975 0.950 0.925 0.900 0.875 0.850 0.825 0.800 No CPU* *No-CPU Mode: The controller enters the no-CPU mode by ramping down the output voltage to 0V with the shutdown slew rate. When exiting the no-CPU mode, the controller ramps the output up to the new VID output voltage using the startup slew rate. In noCPU mode, the controller remains in standby so VID transitions may be detected. ideal transitions, guaranteeing just-in-time arrival at the new output-voltage level with the lowest possible peak currents for a given output capacitance. At the beginning of an output-voltage transition, the MAX8707 blanks both VROK thresholds, preventing the VROK open-drain output from changing states during the transition. The controller enables the lower VROK threshold approximately 20s after the slew-rate controller reaches the target output voltage, but the upper VROK threshold is enabled only if the controller remains in forced-PWM operation. If the controller enters pulseskipping operation, the upper VROK threshold remains blanked. The slew-rate (set by resistor RTIME) must be set fast enough to ensure that the transition can be completed within the maximum allotted time. When transitions occur in pulse-skipping mode, the MAX8707 sets OVP to 1.75V and disables the integrator at the beginning of all transitions. OVP remains at 1.75V and the integrator remains disabled until 20s after the transition is completed (internal target settles) and the output is in regulation (an error-comparator edge is detected). The MAX8707 automatically controls the current to the minimum level required to complete the transition in the calculated time. The slew-rate controller uses an internal capacitor and current source programmed by RTIME to transition the output voltage. The total transition time depends on RTIME, the voltage difference, and the accuracy of the slew-rate controller (CSLEW accuracy). The slew rate is not dependent on the total output capacitance, as long as the surge current is less than the current limit set by ILIM(AVE) and ILIM(PK). For voltage transitions into and out of suspend mode, the transition time (tTRAN) is given by: t TRAN(SUS) = | VNEW - VOLD | dVTARGET / dt where dVTARGET / dt = 6.25mV/s x 143k / RTIME is the slew rate, VOLD is the original output voltage, and VNEW is the new target voltage. See TIME Slew-Rate Accuracy in the Electrical Characteristics for tSLEW limits. For soft-start and shutdown, the controller automatically reduces the slew rate by 1/4th: ______________________________________________________________________________________ 23 Multiphase, Fixed-Frequency Controller for AMD Hammer CPU Core Power Supplies t TRAN(START) = t TRAN(SHDN) = 4 VTARGET dVTARGET / dt When exiting deeper sleep (SUS pulled low), the MAX8707 starts to slew the internal target up towards the new target. The controller remains in skip mode while the output voltage is higher than the internal target. As the internal target approaches the output voltage, the MAX8707 activates all enabled phases (DRSKP driven high) so the output voltage may be ramped up at the slew rate set by RTIME. The controller blanks VROK (forced high impedance) until 20s after the transition is completed. MAX8707 For all dynamic VID transitions, the rate at which the VID inputs (D0-D4) are clocked sets the slew rate, with a maximum slew-rate limit set by the RTIME value. The practical range of RTIME is 47k to 392k corresponding to slew rates of 19mV/s to 2.28mV/s, respectively. The output voltage tracks the slewed target voltage, making the transitions relatively smooth. The average inductor current per phase required to make an output-voltage transition is: IL COUT x (dVTARGET / dt) PH Forced-PWM Operation (Normal Mode) During soft-start, soft-shutdown, and normal operation-- when the CPU is actively running (SKIP = low, Table 5)-- the MAX8707 operates with a low-noise, forced-PWM control scheme. Forced-PWM operation forces DRSKP high, instructing the drivers to disable their zero-crossing comparators and force the low-side gate-drive waveforms to constantly be the complement of the high-side gate-drive waveforms. This keeps the switching frequency constant and allows the inductor current to reverse under light loads, providing fast, accurate negative output-voltage transitions by quickly discharging the output capacitors. Forced-PWM operation comes at a cost: the no-load +5V bias supply current remains between 10mA to 200mA per phase, depending on the external MOSFETs and switching frequency. To maintain high efficiency under light-load conditions, the controller switches to a lowpower pulse-skipping control scheme after entering suspend mode. where dVTARGET / dt is the required slew rate, COUT is the total output capacitance, and PH is the number of active phases. Suspend Transition (Forced-PWM Operation Selected) When the MAX8707 enters suspend mode while configured for forced-PWM operation (SKIP pulled low), the controller ramps the output voltage down to the programmed SUSV voltage at the slew rate determined by RTIME. The controller blanks VROK (forced high impedance) until 20s after the transition is completed--internal target voltage equals the SUSV voltage. After this blanking time expires, the controller automatically shuts down phases 2, 3, and 4 (DRSKP pulled low), and enters single-phase, pulse-skipping operation. VROK monitors only the lower threshold in skip mode. When exiting suspend mode (SUS pulled low), the MAX8707 immediately activates all enabled phases (DRSKP driven high) so the output voltage may be ramped up at the slew rate set by RTIME. The controller blanks VROK (forced high impedance) until 20s after the transition is completed--internal target voltage equals the selected VID-DAC voltage. Suspend Transition (Pulse-Skipping Operation Selected) If the MAX8707 is configured for pulse-skipping operation (SKIP = high) when SUS goes high, the MAX8707 immediately disables phases 2, 3, and 4 (DRSKP pulled low) and enters pulse-skipping operation (Figure 5). The output drops at a rate determined by the load and the output capacitance. The internal target still ramps as before, and VROK remains high impedance until the new target is reached plus an extra 20s. After this time expires, VROK monitors only the lower threshold. 24 Light-Load Pulse-Skipping Operation The MAX8707 includes a light-load operating-mode control input (SKIP) used to disable extra phases and enable/disable the driver's zero-crossing comparator. When the driver's zero-crossing comparators are enabled (DRSKP pulled low), the controller forces PWM_ low for the disabled phases so the driver pulls DL_ low when its current-sense inputs detect zero inductor current. This keeps the inductor from discharging the output capacitors and forces the controller to skip pulses under lightload conditions to avoid overcharging the output. When the zero-crossing comparators are disabled, each controller maintains PWM operation under light-load conditions (forced PWM). After the MAX8707 enters suspend mode while configured for forced-PWM operation (SKIP pulled low), the controller automatically switches to the pulse-skipping control scheme 20s after the target voltage reaches the programmed SUSV voltage. When pulse-skipping operation is enabled, the controller terminates the on-time when the output voltage exceeds the feedback threshold and when the current- ______________________________________________________________________________________ Multiphase, Fixed-Frequency Controller for AMD Hammer CPU Core Power Supplies MAX8707 VID CPU CORE VOLTAGE SUSV SUS INTERNAL PWM CONTROL PWM1 PWM2 PWM3 PWM4 DRSKP FORCED-PWM AUTO 1-PHASE SKIP FORCED-PWM VROK HIGH-Z tBLANK 20s typ LOW THRESHOLD ONLY HIGH-Z tBLANK 20s typ NOTE: OVP CONSTANTLY TRACKS THE INTERNAL TARGET, AND THE INTEGRATOR (CCV) IS CONSTANTLY ENABLED. Figure 4. Suspend Transition in Forced-PWM Mode (SKIP = low) CPU CORE VOLTAGE ACTUAL VOUT TARGET VID SUSV SKIP = SUS INTERNAL PWM CONTROL PWM1 PWM2 PWM3 PWM4 DRSKP 1-PHASE SKIP FORCED PWM VROK OVP/CCV HIGH-Z LOW VROK THRESHOLD ONLY HIGH-Z OVP = 1.8V INTEGRATOR DISABLED tBLANK 20s OVP TRACKS INTERNAL TARGET INTEGRATOR ENABLED tBLANK 20s Figure 5. Suspend Transition in Pulse-Skipping Operation (SKIP = SUS) ______________________________________________________________________________________ 25 Multiphase, Fixed-Frequency Controller for AMD Hammer CPU Core Power Supplies MAX8707 Table 5. SKIP Settings SKIP (INPUT) SUS (INPUT) MODE DRSKP (OUTPUT) OPERATION The controller operates with a constant switching frequency, providing low-noise forced-PWM operation. The controller disables the zero-crossing comparators, forcing the low-side gate-drive waveform to constantly be the complement of the high-side gate-drive waveform. The controller automatically switches to pulse-skipping operation 20s after the target voltage reaches the SUSV voltage. Pulse-skipping operation forces the controller into PFM operation under light loads. Phase 1 remains active while the other three phases are disabled--PWM2, PWM3, and PWM4 pulled low. Pulse-skipping operation forces the controller into PFM operation under light loads. Phase 1 remains active while the other three phases are disabled--PWM2, PWM3, and PWM4 pulled low. Low (GND) Low (GND) High (3.3V or VCC) Multiphase Forced-PWM High (VDD) 1-Phase Pulse Skipping Low (PGND) High (>1.2V) Don't Care 1-Phase Pulse Skipping Low (PGND) sense voltage exceeds the Idle Mode current-sense threshold (VIDLE = 0.1 x VPKLIMIT). Under heavy-load conditions, the continuous inductor current remains above the Idle-Mode current-sense threshold, so the on-time depends only on the feedback-voltage threshold. Under light-load conditions, the controller remains above the feedback-voltage threshold, so the on-time duration depends solely on the Idle-Mode currentsense threshold, which is approximately 10% of the fullload current-limit threshold set by ILIM(PK). When the controller enters suspend mode while SKIP is pulled high, the multiphase controller immediately disables three phases, and only the main phase (PWM1) remains active. When pulse skipping, the controller blanks the upper VROK threshold and the OVP threshold tracks the selected VID DAC code. The MAX8707 automatically uses forced-PWM operation during soft-start and soft-shutdown, regardless of the SKIP configuration. Idle-Mode Current Sense Threshold The Idle-Mode current-sense threshold forces a lightly loaded regulator to source a minimum amount of energy with each on-time since the controller cannot terminate the on-time until the current-sense voltage exceeds the Idle-Mode current-sense threshold (VIDLE = 0.1 x VPKLIMIT). Since the zero-crossing comparator prevents the switching regulator from sinking current, the controller must skip pulses to avoid overcharging the output. When the clock edge occurs, if the output voltage still exceeds the feedback threshold, the conIdle Mode is a trademark of Maxim Integrated Products, Inc. 26 troller does not initiate another on-time. This forces the controller to actually regulate the valley of the output voltage ripple under light-load conditions. Automatic Pulse-Skipping Crossover In skip mode, the MAX8707 disables three phases and forces DRSKP low to instruct the skip-mode drivers to activate their zero-crossing comparators. Therefore, an inherent automatic switchover to PFM takes place at light loads (Figure 6), resulting in a highly efficient operating mode. This switchover is affected by a comparator that truncates the low-side switch on-time at the inductor current's zero crossing. The driver's zero-crossing comparator senses the inductor current across the low-side MOSFET (refer to the skip-mode driver data sheet). Once V LX - V PGND drops below the zero-crossing threshold, the driver forces DL low. This mechanism causes the threshold between pulse-skipping PFM and nonskipping PWM operation to coincide with the boundary between continuous and discontinuous inductor-current operation (also known as the critical conduction point). The load-current level at which the PFM/PWM crossover occurs, ILOAD(SKIP), is given by: ILOAD(SKIP) = VOUT ( VIN - VOUT ) 2VINfSW L The switching waveforms may appear noisy and asynchronous when light loading causes pulse-skipping operation, but this is a normal operating condition that ______________________________________________________________________________________ Multiphase, Fixed-Frequency Controller for AMD Hammer CPU Core Power Supplies results in high light-load efficiency. Trade-offs in PFM noise vs. light-load efficiency are made by varying the inductor value. Generally, low inductor values produce a broader efficiency vs. load curve, while higher values result in higher full-load efficiency (assuming that the coil resistance remains fixed) and less output voltage ripple. Penalties for using higher inductor values include larger physical size and degraded load-transient response (especially at low input-voltage levels). MAX8707 tON(SKIP) = VOUT VINfSW IIDLE INDUCTOR CURRENT ILOAD ILOAD(SKIP) 2 Current Sense The output current of each phase is sensed differentially. Each phase of the MAX8707 has an independent return path for fully differential current-sense. A low offset voltage and high-gain (10V/V) differential current amplifier at each phase allow low-resistance currentsense resistors to be used to minimize power dissipation. Sensing the current at the output of each phase offers advantages, including less noise sensitivity, more accurate current sharing between phases, and the flexibility of using either a current-sense resistor or the DC resistance of the output inductor. Using the DC resistance (RDCR) of the output inductor allows higher efficiency. In this configuration, the initial tolerance and temperature coefficient of the inductor's DCR must be accounted for in the output-voltage droop-error budget. This current-sense method uses an RC filtering network to extract the current information from the output inductor (Figure 7). The time constant of the RC network should match the inductor's time constant (L/RDCR): L = REQ CSENSE RDCR where CSENSE is the sense capacitor and REQ is the equivalent sense resistance. To minimize the currentsense error due to the current-sense inputs' bias current (ICSP_ and ICSN_), choose REQ less than 2k and use the above equation to determine the sense capacitance (CSENSE). Choose capacitors with 5% tolerance and resistors with 1% tolerance specifications. Temperature compensation is recommended for this current-sense method. When using a current-sense resistor for accurate output-voltage positioning (CRSP to CRSN for the MAX8707), differential RC-filter circuits should be used to cancel the equivalent series inductance of the current-sense resistor (Figure 7). Similar to inductor DCRsensing methods, the RC filter's time constant should match the L/R time constant formed by the currentsense resistor's parasitic inductance: 0 ON-TIME TIME Figure 6. Pulse-Skipping/Discontinuous Crossover Point LESL = REQ CSENSE RSENSE where LESL is the equivalent series inductance of the current-sense resistor, R SENSE is the current-sense resistance value, CSENSE is the compensation capacitor, and REQ is the equivalent compensation resistance. Current Balance The fixed-frequency, multiphase, current-mode architecture automatically forces the individual phases to remain current balanced. After the oscillator triggers an on-time, the controller does not terminate the on-time until the amplified differential current-sense voltage reaches the integrated threshold voltage (VREF - VTRC). This control scheme regulates the peak inductor current of each phase, forcing them to remain properly balanced. Therefore, the average inductor-current variation depends mainly on the variation in the currentsense element and inductance value. Peak/Average Current Limit The MAX8707 current-limit circuit employs a fast peak inductor current-sensing algorithm. Once the currentsense signal (CSP to CSN) of the active phase exceeds the peak current-limit threshold, the PWM controller terminates the on-time. The MAX8707 also includes a slower average current sense that uses a current-sense resistor between CRSP and CRSN to accurately limit the inductor current. When this average current-sense threshold is exceeded, the current-limit circuit lowers the peak current-limit threshold, effectively lowering the average inductor current. See the Current Limit section in the Design Procedure section. 27 ______________________________________________________________________________________ Multiphase, Fixed-Frequency Controller for AMD Hammer CPU Core Power Supplies MAX8707 INPUT (VIN) CIN CIN INPUT (VIN) DRIVER NH L LX DL PWM PGND NL DL PWM COUT RSENSE DRIVER NH INDUCTOR L LX DL PGND NL DL REQ CSENSE COUT RDCR DH DH PWM_ CSP_ CSN_ PWM_ CSP_ CSN_ CONTROLLER A) OUTPUT SERIES RESISTOR SENSING CONTROLLER B) LOSSLESS INDUCTOR SENSING Figure 7. Current-Sense Methods Power-Up Sequence (POR, UVLO) Power-on reset (POR) occurs when VCC rises above approximately 2V, resetting the fault latch and preparing the controller for operation. The VCC undervoltagelockout (UVLO) circuitry inhibits switching--forces DRSKP high and pulls the PWM_ outputs low--until VCC rises above 4.25V. The controller powers up the reference once the system enables the controller--VCC above 4.25V and SHDN pulled high. With the reference in regulation, the controller begins to slew the output voltage to the target voltage--either the output of the VID DAC (SUS = low) or the SUSV suspend voltage (SUS = high)--at 1/4th the slew rate set by RTIME: t TRAN(START) = 4 VTARGET dVTARGET / dt down until the fault latch is cleared by toggling SHDN or cycling the VCC power supply below 1V. If the VCC voltage drops below 4.25V, the controller assumes that there is not enough supply voltage to make valid decisions. To protect the output from overvoltage faults, the controller shuts down immediately-- forces DRSKP high and pulls the PWM_ outputs low. Shutdown When SHDN goes low, the MAX8707 enters low-power shutdown mode. VROK is pulled low immediately, and the output voltage ramps down at 1/4th the slew rate set by RTIME: t TRAN(SHDN) = 4 VOUT dVTARGET / dt where dVTARGET / dt = 6.25mV/s x 143k / RTIME is the slew rate. The soft-start circuitry does not use a variable current limit, so full output current is available immediately. VROK becomes high impedance approximately 20s after the MAX8707 reaches the target voltage. For automatic startup, the battery voltage should be present before VCC. If the controller attempts to bring the output into regulation without the battery voltage present, the fault latch trips. The controller remains shut where dVTARGET / dt = 6.25mV/s x 143k / RTIME is the slew rate. Slowly discharging the output capacitors by slewing the output over a long period of time keeps the average negative inductor current low (damped response), thereby eliminating the negative output voltage excursion that occurs when the controller discharges the output quickly by permanently turning on the low-side MOSFET (underdamped response). This eliminates the need for the Schottky diode normally connected between the output and ground to clamp 28 ______________________________________________________________________________________ Multiphase, Fixed-Frequency Controller for AMD Hammer CPU Core Power Supplies MAX8707 VCC SHDN VID (D0-D4) INVALID CODE INVALID CODE SOFT-SHUTDOWN 1/4TH SLEW RATE SET BY RTIME SOFT-START 1/4TH SLEW RATE SET BY RTIME VCORE INTERNAL PWM CONTROL DRSKP FORCED-PWM FORCED-PWM VROK tBLANK 20s typ tBLANK 20s typ Figure 8. Power-Up and Shutdown Sequence Timing Diagram the negative output-voltage excursion. When the controller reaches the 0V target, the drivers are disabled (DRSKP driven low and PWM_ outputs pulled low), the reference turns off, and the supply current drops to about 10A (max). When a fault condition--output UVLO or thermal shutdown--activates the shutdown sequence, the protection circuitry sets the fault latch to prevent the controller from restarting. To clear the fault latch and reactivate the controller, toggle SHDN or cycle VCC power below 1V. Fault Protection Output Overvoltage Protection (Unlatched) The overvoltage-protection (OVP) circuit is designed to protect the CPU against a shorted high-side MOSFET by drawing high current and blowing the battery fuse. The MAX8707 continuously monitors the output for an overvoltage fault. The controller detects an OVP fault if the output voltage exceeds the set target voltage by more than 200mV. After entering pulse-skipping operation (SKIP rising edge), the OVP threshold is set to 1.75V until the output voltage drops below the target voltage for the first time. Once the MAX8707 detects the output is being regulated (VOUT VTARGET), the OVP threshold begins tracking the target voltage again. When the OVP circuit detects an overvoltage fault, it immediately enters forced-PWM operation--pulling DRSKP high so the drivers force the low-side gate dri- vers high (DL = VDD) and pull the high-side gate drivers low (DH = LX). The controller does not initiate an on-time pulse until the output voltage drops below the OVP threshold. This action turns on the synchronousrectifier MOSFET with 100% duty and, in turn, rapidly discharges the output filter capacitor and forces the output low. If the condition that caused the overvoltage (such as a shorted high-side MOSFET) persists, the battery fuse blows. Overvoltage protection can be disabled through the nofault test mode (see the No-Fault Test Mode section). Output Undervoltage Protection (Latched) The output undervoltage-protection (UVP) function is similar to foldback current limiting, but employs a timer rather than a variable current limit. If the MAX8707 output voltage is under 70% of the nominal value, the controller activates the shutdown sequence and sets the fault latch. Once the controller ramps down to the 0V setting, it forces the PWM_ driver outputs low. Toggle SHDN or cycle the VCC power supply below 1V to clear the fault latch and reactivate the controller. UVP can be disabled through the no-fault test mode (see the No-Fault Test Mode section). Thermal Fault Protection (Latched) The MAX8707 features a thermal fault-protection circuit. When the junction temperature rises above +160C, a 29 ______________________________________________________________________________________ Multiphase, Fixed-Frequency Controller for AMD Hammer CPU Core Power Supplies MAX8707 thermal sensor sets the fault latch and activates the soft-shutdown sequence. Once the controller ramps down to the 0V setting, it forces the PWM_ driver outputs low. Toggle SHDN or cycle the VCC power supply below 1V to clear the fault latch and reactivate the controller after the junction temperature cools by 15C. Thermal shutdown can be disabled through the no-fault test mode (see the No-Fault Test Mode section). No-Fault Test Mode The latched fault protection features can complicate the process of debugging prototype breadboards since there are (at most) a few milliseconds in which to determine what went wrong. Therefore, a no-fault test mode is provided to disable the fault protection--overvoltage protection, undervoltage protection, and thermal shutdown. Additionally, the test mode clears the fault latch if it has been set. The no-fault test mode is entered by forcing 11V to 13V on SHDN. where PH is the total number of active phases. Switching Frequency: This choice determines the basic trade-off between size and efficiency. The optimal frequency is largely a function of maximum input voltage, due to MOSFET switching losses that are proportional to frequency and VIN2. The optimum frequency is also a moving target, due to rapid improvements in MOSFET technology that are making higher frequencies more practical. Inductor Operating Point: This choice provides tradeoffs between size vs. efficiency and transient response vs. output noise. Low inductor values provide better transient response and smaller physical size, but also result in lower efficiency and higher output noise due to increased ripple current. The minimum practical inductor value is one that causes the circuit to operate at the edge of critical conduction (where the inductor current just touches zero with every cycle at maximum load). Inductor values lower than this grant no further sizereduction benefit. The optimum operating point is usually found between 20% and 50% ripple current. Multiphase, Fixed-Frequency Design Procedure Firmly establish the input voltage range and maximum load current before choosing a switching frequency and inductor operating point (ripple-current ratio). The primary design trade-off lies in choosing a good switching frequency and inductor operating point, and the following four factors dictate the rest of the design: Input Voltage Range: The maximum value (VIN(MAX)) must accommodate the worst-case high AC-adapter voltage. The minimum value (VIN(MIN)) must account for the lowest input voltage after drops due to connectors, fuses, and battery selector switches. If there is a choice at all, lower input voltages result in better efficiency. Maximum Load Current: There are two values to consider. The peak load current (ILOAD(MAX)) determines the instantaneous component stresses and filtering requirements, and thus drives output capacitor selection, inductor saturation rating, and the design of the current-limit circuit. The continuous load current (ILOAD) determines the thermal stresses and thus drives the selection of input capacitors, MOSFETs, and other critical heat-contributing components. Modern notebook CPUs generally exhibit ILOAD = ILOAD(MAX) x 80%. For multiphase systems, each phase supports a fraction of the load, depending on the current balancing. When properly balanced, the load current is evenly distributed among each phase: I ILOAD(PHASE) = LOAD PH Inductor Selection The switching frequency and operating point (% ripple current or LIR) determine the inductor value as follows: V VIN - VOUT OUT L = PH fSW ILOAD(MAX) LIR VIN where PH is the total number of phases, and fSW is the switching frequency per phase. Find a low-loss inductor with the lowest possible DC resistance that fits in the allotted dimensions. If using a swinging inductor (where the no-load inductance decreases linearly with increasing current), evaluate the LIR with properly scaled inductance values. For the selected inductance value, the actual peak-to-peak inductor ripple current (IINDUCTOR) is defined by: V (V - V ) IINDUCTOR = OUT IN OUT VIN fSW L Ferrite cores are often the best choice, although powdered iron is inexpensive and can work well at 200kHz. The core must be large enough not to saturate at the peak inductor current (IPEAK): ILOAD(MAX) IINDUCTOR IPEAK = + PH 2 30 ______________________________________________________________________________________ Multiphase, Fixed-Frequency Controller for AMD Hammer CPU Core Power Supplies Current Limit Peak Inductor Current Limit (ILIM(PK)) The MAX8707 overcurrent protection employs a peak current-sensing algorithm that uses either currentsense resistors or the inductor's DCR as the currentsense element (see the Current Sense section). Since the controller limits the peak inductor current, the maximum average load current is less than the peak current-limit threshold by an amount equal to half the inductor ripple current. Therefore, the maximum load capability is a function of the current-sense resistance, inductor value, switching frequency, and input voltage. When combined with the undervoltage-protection circuit, this current-limit method is highly effective. The peak current-limit threshold is set with a single external resistor between ILIM(PK) and analog ground, where the resistor is determined by the following equation: RILIM(PK) = 8V x RTRC IPKLIMIT RSENSE 1/20th the voltage difference between ILIM(AVE) and the reference: VLAVE = VREF - VILIM( AVE) 20 MAX8707 The logic threshold for switchover to the 25mV default value is approximately VCC - 1V. The average currentlimit circuit also prevents against excessive reverse inductor current when VOUT is sinking current. The negative current-limit threshold is equivalent to the positive current limit, and tracks the positive current limit when VLAVE is adjusted. Output-Capacitor Selection The output filter capacitor must have low enough effective series resistance (ESR) to meet output ripple and load-transient requirements. In CPU VCORE converters and other applications where the output is subject to large load transients, the output capacitor's size typically depends on how much ESR is needed to prevent the output from dipping too low under a load transient. Ignoring the sag due to finite capacitance: (RESR + RPCB ) VSTEP ILOAD(MAX) where RSENSE is the resistance value of the currentsense element (inductors' DCR or current-sense resistor), RTRC is the resistance between TRC and REF, and IPKLIMIT is the desired peak current limit (per phase). The peak current-limit-threshold voltage adjustment range is from 20mV to 80mV. The peak current-limit circuit also prevents excessive reverse inductor currents when VOUT is sinking current. The negative current-limit threshold is equivalent to the positive current limit, and tracks the positive current limit when RILIM(PK) or RTRC are adjusted. When a phase drops below the negative current limit, the controller activates an on-time pulse at the next clock edge, regardless of the error-amplifier state, until the inductor current rises above the negative current-limit threshold. Average Inductor Current-Limit (ILIM(AVE)) The MAX8707 also uses the accurate CRSP to CRSN current-sense voltage to limit the average current per phase. When the average current-limit threshold is exceeded, the controller internally reduces the peak inductor current-limit threshold (ILIM(PK)) until the average current remains within the programmed limits. When the accurate current sensing is disabled (CRSP = VCC), the average current-limit circuit is disabled. The average current-limit threshold defaults to 25mV if ILIM(AVE) is connected to VCC. In adjustable mode, the average current-limit threshold voltage is precisely In non-CPU applications, the output capacitor's size often depends on how much ESR is needed to maintain an acceptable level of output ripple voltage. The output ripple voltage of a step-down controller equals the total inductor ripple current multiplied by the output capacitor's ESR. When operating multiphase systems out-ofphase, the peak inductor currents of each phase are staggered, resulting in lower output ripple voltage (VRIPPLE) by reducing the total inductor ripple current. For nonoverlapping, multiphase operation (VIN PH x VOUT), the maximum ESR to meet the output-ripplevoltage requirement is: VIN fSW L RESR VRIPPLE (VIN - PH VOUT )VOUT where PH is the total number of active phases, and fSW is the switching frequency per phase. The actual capacitance value required relates to the physical size needed to achieve low ESR, as well as to the chemistry of the capacitor technology. Thus, the capacitor selection is usually limited by ESR and voltage rating rather than by capacitance value (this is true of polymer types). ______________________________________________________________________________________ 31 Multiphase, Fixed-Frequency Controller for AMD Hammer CPU Core Power Supplies The capacitance value required is determined primarily by the output transient-response requirements. Low inductor values allow the inductor current to slew faster, replenishing the charge removed from or added to the output filter capacitors by a sudden load step. Therefore, the amount of output soar when the load is removed is a function of the output voltage and inductor value. The minimum output capacitance required to prevent overshoot (VSOAR) due to stored inductor energy can be calculated as: COUT (ILOAD(MAX) )2 L 2PH VOUT VSOAR MAX8707 Setting Voltage Positioning Voltage positioning dynamically lowers the output voltage in response to the load current, reducing the output capacitance and processor's power-dissipation requirements. The controller uses two transconductance amplifiers to set the transient and DC output voltage droop (Figure 2). The transient-compensation (TRC) amplifier determines how quickly the MAX8707 responds to the load transient. The slower voltage-positioning (VPS) amplifier adjusts the steady-state regulation voltage as a function of the load. This adjustability allows flexibility in the selected current-sense resistor value or inductor DCR, and allows smaller currentsense resistance to be used, reducing the overall power dissipated. Steady-State Voltage Positioning Connect a resistor (RVPS) between VPS and FBS to set the DC steady-state droop (load line) based on the required DC voltage-positioning slope (RDROOP): RVPS = RDROOP RSENSE GM(VPS) where PH is the total number of active phases. When using low-capacity ceramic filter capacitors, capacitor size is usually determined by the capacity needed to prevent V SOAR from causing problems during load transients. Generally, once enough capacitance is added to meet the overshoot requirement, undershoot at the rising load edge is no longer a problem. Input Capacitor Selection The input capacitor must meet the ripple-current requirement (IRMS) imposed by the switching currents. The multiphase controllers operate out-of-phase, which reduces the RMS input current by dividing the input current between several staggered stages. For duty cycles less than 100%/PH per phase, the IRMS requirements can be determined by the following equation: I IRMS = LOAD PHVOUT (VIN - PHVOUT ) PHVIN where PH is the total number of out-of-phase switching regulators. The worst-case RMS current requirement occurs when operating with VIN = 2PH VOUT. At this point, the above equation simplifies to I RMS = 0.5 x ILOAD / PH. For most applications, nontantalum chemistries (ceramic, aluminum, or OS-CON) are preferred due to their resistance to inrush surge currents, typical of systems with a mechanical switch or connector in series with the input. If the MAX8707 is operated as the second stage of a two-stage power-conversion system, tantalum input capacitors are acceptable. In either configuration, choose an input capacitor that exhibits less than 10C temperature rise at the RMS input current for optimal circuit longevity. where the current-sense resistance (RSENSE) depends on the current-sense method, and the voltage-positioning amplifier's transconductance (GM(VPS)) is typically 200S as defined in the Electrical Characteristics table. When the MAX8707 CRS sensing is enabled, RSENSE is defined as the accurate CRS current-sense resistance: RSENSE = RCRS when CRS sensing is enabled. When the MAX8707 CRS sensing is disabled, the controller sums together the input signals of the currentsense inputs (CSP_, CSN_). These inputs typically use the inductors' DC resistance (RDCR) to sense the current, so RSENSE is defined as the average of the effective CS current-sense resistances (see the Current Sense section): RSENSE = RDCR when CRS sensing is disabled. When the inductors' DCR (RDCR) is used as the current-sense elements (for lossless sensing), RVPS should include an NTC thermistor to minimize the temperature dependence of the voltage-positioning slope. To avoid output-voltage errors caused by the voltagepositioning current, a second transconductance amplifier generates an equivalent current on the FBS input. Accurate MAX8707 CRS sensing is disabled by connecting CRSP to VCC. 32 ______________________________________________________________________________________ Multiphase, Fixed-Frequency Controller for AMD Hammer CPU Core Power Supplies Disable voltage positioning by shorting VPS directly to FBS. Transient Droop Connect a resistor (RTRC) between TRC and REF to set the transient droop (RDROOP(AC)) based on the voltagepositioning requirements. TRC allows the controller to quickly respond to load transients, but it does not affect the DC steady-state droop. Choose RTRC based on the equation: RTRC = RTRANSRCS PHRDROOP( AC) the controller to effectively operate with a lower switching frequency. This results in an input threshold voltage at which the controller begins to skip pulses (VIN(SKIP)): 1 VIN(SKIP) = VOUT fSW t ON(MIN) where fSW is the switching frequency per phase selected by OSC, and tON(MIN) is 110ns plus the driver's turn-off delay (PWM low to LX low) minus the driver's turn-on delay (PWM high to LX high). For the best highvoltage performance, use the slowest switching-frequency setting (200kHz per phase, OSC = GND). MAX8707 where RCS is the current-sense element connected from CSP_ to CSN_ (which is typically the inductor's effective DCR: RCS = L / REQCSENSE), RTRANS is the currentsense amplifier gain divided by the transient amplifier's transconductance as defined in the Electrical Characteristics table, and RDROOP(AC) is typically 80% of the DC voltage-positioning slope to minimize the transient sag voltage. The TRC resistance also sets the small-signal loop gain, so a maximum RTRC value is required for stability, even if voltage positioning is not used (VPS = FBS). VRIPPLE RTRC < (RTRANS RSENSE IL) / 3 TRC is high impedance in shutdown. PC Board Layout Guidelines Careful PC board layout is critical to achieve low switching losses and clean, stable operation. The switching power stage requires particular attention (Figure 9). If possible, mount all of the power components on the top side of the board with their ground terminals flush against one another. Follow these guidelines for good PC board layout: 1) Keep the high-current paths short, especially at the ground terminals. This is essential for stable, jitterfree operation. 2) Connect all analog grounds to a separate solid copper plane, which connects to the GND pin of the controller. This includes the VCC bypass capacitor, REF and GNDS bypass capacitors, compensation (CCV, TRC) components, and the resistive dividers connected to ILIM(AVE), SUSV, and OFS. 3) Keep the power traces and load connections short. This is essential for high efficiency. The use of thick copper PC boards (2oz vs. 1oz) can enhance fullload efficiency by 1% or more. Correctly routing PC board traces is a difficult task that must be approached in terms of fractions of centimeters, where a single m of excess trace resistance causes a measurable efficiency penalty. 4) Connections for current limiting (CSP_, CSN_) and voltage positioning (CRSP, CRSN) must be made using Kelvin-sense connections to guarantee the current-sense accuracy. 5) Route high-speed switching nodes and driver traces away from sensitive analog areas (REF, CCV, TRC, VPS, etc.). Make all pin-strap control input connections (SHDN, SKIP, SUS, OSC) to analog ground or VCC rather than power ground or VDD. 6) Keep the drivers close to the MOSFET, with the gate-drive traces (DL, DH, LX, and BST) short and wide to minimize trace resistance and inductance. 33 Applications Information Duty-Cycle Limits Minimum Input Voltage The minimum input operating voltage (dropout voltage) is restricted by stability requirements, not the minimum off-time (tOFF(MIN)). The MAX8707 does not include slope compensation, so the controller becomes unstable with duty cycles greater than 50% per phase: VIN(MIN) 2VOUT(MAX) However, the controller may briefly operate with duty cycles over 50% during heavy load transients. Maximum Input Voltage The MAX8707 controller and driver has a minimum ontime, which determines the maximum input operating voltage that maintains the selected switching frequency. With higher input voltages, each pulse delivers more energy than the output is sourcing to the load. At the beginning of each cycle, if the output voltage is still above the feedback threshold voltage, the controller does not trigger an on-time pulse resulting in pulseskipping operation regardless of the operating mode selected by SKIP. This allows the controller to maintain regulation above the maximum input voltage, but forces ______________________________________________________________________________________ Multiphase, Fixed-Frequency Controller for AMD Hammer CPU Core Power Supplies MAX8707 KELVIN SENSE VIAS UNDER THE SENSE RESISTOR (REFER TO THE EVALUATION KIT) CPU RSENSE OUTPUT COUT COUT COUT COUT COUT INDUCTOR INDUCTOR INDUCTOR COUT INDUCTOR POWER GROUND CIN CIN CIN CIN CIN POWER GROUND INPUT ANALOG GROUND (INNER LAYER) CONNECT GND AND PGND TO THE CONTROLLER AT ONE POINT ONLY AS SHOWN PLACE CONTROLLER ON BACKSIDE WHEN POSSIBLE, USING THE GROUND PLANE TO SHIELD THE IC FROM EMI CONNECT THE EXPOSED PAD TO ANALOG GND POWER GROUND (INNER LAYER) Figure 9. PC Board Layout Example 34 ______________________________________________________________________________________ CIN Multiphase, Fixed-Frequency Controller for AMD Hammer CPU Core Power Supplies This is essential for high-power MOSFETs that require low-impedance gate drivers to avoid shootthrough currents. 7) When trade-offs in trace lengths must be made, it's preferable to allow the inductor charging path to be made longer than the discharge path. For example, it's better to allow some extra distance between the input capacitors and the high-side MOSFET than to allow distance between the inductor and the lowside MOSFET or between the inductor and the output filter capacitor. ground planes: input/output ground, where all the high-power components go; the power ground plane, where the PGND pin, VDD bypass capacitor, and driver IC ground connection go; and the controller's analog ground plane, where sensitive analog components, the master's GND pin, and the VCC bypass capacitor go. The controller's analog ground plane (GND) must meet the power ground plane (PGND) only at a single point directly beneath the IC. The power ground plane should connect to the high-power output ground with a short, thick metal trace from PGND to the source of the low-side MOSFETs (the middle of the star ground). 5) Connect the output power planes (VCORE and system ground planes) directly to the output-filtercapacitor positive and negative terminals with multiple vias. Place the entire DC-DC converter circuit as close to the CPU as is practical. MAX8707 Layout Procedure 1) Place the power components first, with ground terminals adjacent (low-side MOSFET source, CIN, COUT, and D1 anode). If possible, make all these connections on the top layer with wide, copper-filled areas. 2) Mount the driver IC adjacent to the low-side MOSFETs. The DL gate traces must be short and wide (50mils to 100mils wide if the MOSFET is 1in from the driver IC). 3) Group the gate-drive components (BST diodes and capacitors, VDD bypass capacitor) together near the driver IC. 4) Make the DC-DC controller ground connections as shown in the Standard Application Circuits. This diagram can be viewed as having three separate ______________________________________________________________________________________ 35 Multiphase, Fixed-Frequency Controller for AMD Hammer CPU Core Power Supplies MAX8707 Pin Configuration TOP VIEW Chip Information TRANSISTOR COUNT: 9011 PROCESS: BiCMOS CSN3 CSN4 CSN2 CSP2 CSN1 CSP4 40 39 38 37 36 35 34 33 32 31 D2 D3 D4 N.C. SKIP SHDN SUS SUSV ILIM(AVE) 1 2 3 4 5 6 7 8 9 30 CRSP 29 CRSN 28 VPS 27 FBS 26 DRSKP MAX8707 CSP3 D0 CSP1 25 PWM4 24 PWM3 23 PWM2 22 PWM1 21 VCC OFS 10 11 12 13 14 15 16 17 18 19 20 D1 ILIM(PK) TIME OSC REF GNDS THIN QFN 6mm x 6mm 36 ______________________________________________________________________________________ PGND VROK TRC GND CCV Multiphase, Fixed-Frequency Controller for AMD Hammer CPU Core Power Supplies Package Information (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.) QFN THIN 6x6x0.8.EPS MAX8707 D2 D D/2 k C L b D2/2 E/2 E2/2 E (NE-1) X e C L E2 k e (ND-1) X e L e L C L C L L1 L L e e A1 A2 A PACKAGE OUTLINE 36, 40, 48L THIN QFN, 6x6x0.8mm 21-0141 E 1 2 NOTES: 1. DIMENSIONING & TOLERANCING CONFORM TO ASME Y14.5M-1994. 2. ALL DIMENSIONS ARE IN MILLIMETERS. ANGLES ARE IN DEGREES. 3. N IS THE TOTAL NUMBER OF TERMINALS. 4. THE TERMINAL #1 IDENTIFIER AND TERMINAL NUMBERING CONVENTION SHALL CONFORM TO JESD 95-1 SPP-012. DETAILS OF TERMINAL #1 IDENTIFIER ARE OPTIONAL, BUT MUST BE LOCATED WITHIN THE ZONE INDICATED. THE TERMINAL #1 IDENTIFIER MAY BE EITHER A MOLD OR MARKED FEATURE. 5. DIMENSION b APPLIES TO METALLIZED TERMINAL AND IS MEASURED BETWEEN 0.25 mm AND 0.30 mm FROM TERMINAL TIP. 6. ND AND NE REFER TO THE NUMBER OF TERMINALS ON EACH D AND E SIDE RESPECTIVELY. 7. DEPOPULATION IS POSSIBLE IN A SYMMETRICAL FASHION. 8. COPLANARITY APPLIES TO THE EXPOSED HEAT SINK SLUG AS WELL AS THE TERMINALS. 9. DRAWING CONFORMS TO JEDEC MO220, EXCEPT FOR 0.4mm LEAD PITCH PACKAGE T4866-1. 10. WARPAGE SHALL NOT EXCEED 0.10 mm. PACKAGE OUTLINE 36, 40, 48L THIN QFN, 6x6x0.8mm 21-0141 E 2 2 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 37 (c) 2004 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products. |
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